From cbcd97695580fd7fcb5467b7d37881c301b8783c Mon Sep 17 00:00:00 2001 From: jc_gargma Date: Wed, 25 Dec 2019 12:49:33 -0800 Subject: Rebuild with hotfixes --- ...M-as-default-also-for-Intel-Ice-Lake-xHCI.patch | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 0018-xhci-pci-Allow-host-runtime-PM-as-default-also-for-Intel-Ice-Lake-xHCI.patch (limited to '0018-xhci-pci-Allow-host-runtime-PM-as-default-also-for-Intel-Ice-Lake-xHCI.patch') diff --git a/0018-xhci-pci-Allow-host-runtime-PM-as-default-also-for-Intel-Ice-Lake-xHCI.patch b/0018-xhci-pci-Allow-host-runtime-PM-as-default-also-for-Intel-Ice-Lake-xHCI.patch new file mode 100644 index 0000000..12130cc --- /dev/null +++ b/0018-xhci-pci-Allow-host-runtime-PM-as-default-also-for-Intel-Ice-Lake-xHCI.patch @@ -0,0 +1,48 @@ +From 74641e1ede93144485509cb7c2c682602107ec6b Mon Sep 17 00:00:00 2001 +From: Mika Westerberg +Date: Fri, 15 Nov 2019 18:50:03 +0200 +Subject: xhci-pci: Allow host runtime PM as default also for Intel Ice Lake + xHCI + +Intel Ice Lake has two xHCI controllers one on PCH and the other as part +of the CPU itself. The latter is also part of the so called Type C +Subsystem (TCSS) sharing ACPI power resources with the PCIe root ports +and the Thunderbolt controllers. In order to put the whole TCSS block +into D3cold the xHCI needs to be runtime suspended as well when idle. + +For this reason allow runtime PM as default for Ice Lake TCSS xHCI +controller. + +Signed-off-by: Mika Westerberg +Signed-off-by: Mathias Nyman +Link: https://lore.kernel.org/r/1573836603-10871-5-git-send-email-mathias.nyman@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-pci.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c +index 1904ef56f61c..2907fe4d78dd 100644 +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -48,6 +48,7 @@ + #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 + #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec + #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 ++#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 + + #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 + #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba +@@ -212,7 +213,8 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) + pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || + pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || + pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || +- pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI)) ++ pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || ++ pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI)) + xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; + + if (pdev->vendor == PCI_VENDOR_ID_ETRON && +-- +cgit v1.2.1-1-g437b + -- cgit v1.2.1