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Diffstat (limited to 'zen2-workaround.patch')
| -rw-r--r-- | zen2-workaround.patch | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/zen2-workaround.patch b/zen2-workaround.patch new file mode 100644 index 0000000..ff15362 --- /dev/null +++ b/zen2-workaround.patch @@ -0,0 +1,29 @@ +------------------------------------------------------------------------ +r23262 | Imarok | 2019-12-19 18:52:47 +0200 (Thu, 19 Dec 2019) | 9 lines + +Workaround for L3 cache detection of Ryzen 3000 + +This code is planned to get refactored or removed anyway, so just do a cheap workaround. + +Reviewed by: Imarok +Fixes: #4360 +Differential Revision: https://code.wildfiregames.com/D2353 + + + +Index: source/lib/sysdep/arch/x86_x64/cache.cpp +=================================================================== +--- source/lib/sysdep/arch/x86_x64/cache.cpp (revision 23261) ++++ source/lib/sysdep/arch/x86_x64/cache.cpp (revision 23262) +@@ -89,7 +89,8 @@ + static const size_t associativityTable[16] = + { + 0, 1, 2, 0, 4, 0, 8, 0, +- 16, 0, 32, 48, 64, 96, 128, x86_x64::Cache::fullyAssociative ++ // TODO: The second '16' does not obey to the specifications and is only a workaround. For a correct implementation please look here: https://community.amd.com/thread/244207 ++ 16, 16, 32, 48, 64, 96, 128, x86_x64::Cache::fullyAssociative + }; + + static x86_x64::Cache L2Cache(u32 reg, x86_x64::Cache::Type type) + +------------------------------------------------------------------------ |